A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop
نویسندگان
چکیده
منابع مشابه
High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
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in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...
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Amnon Yariv California Institute of Technology Department of Applied Physics and California Institute of Technology Department of Electrical Engineering 1200 East California Boulevard 128-95 Pasadena, California 91125 Abstract. The bandwidth and residual phase noise of optical phaselocked loops (OPLLs) using semiconductor lasers are typically constrained by the nonuniform frequency modulation r...
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ژورنال
عنوان ژورنال: Circuits and Systems
سال: 2015
ISSN: 2153-1285,2153-1293
DOI: 10.4236/cs.2015.61002